1. Field of Invention
The present invention relates to computer architecture in an X-86 system such as a central processing unit (CPU) that can convert an effective address (EA) or logical address into a physical address (PA), and more particularly to a computer address translation system and the translating method.
2. Description of Related Art
Through the use of virtual memory, the X-86 type of computer architecture is now capable of achieving exceptionally high reading and writing speed. Therefore, virtual memory has become an indispensable part of the computer system. However, the address in a virtual memory is implicitly or explicitly programmed by the user into a word referred to as the effective address, hence the effective address must be translated and mapped into a physical address in an actual memory unit to make the virtual memory system compatible. In general, the amount of mappings in translating from effective address to physical address can be very large. To speed up the translating process, address translation is executed using a high-speed memory unit within the CPU. The high-speed memory unit is known as a translation lookaside buffer (TLB). TLB is a special cache memory for address translation whose input is the effective address and the output is the physical address. Generation of the physical address is largely determined by the result of comparing the linear address (LA) to a tag memory residing within the TLB. The tag memory is a content addressable memory (CAM).
FIG. 1 is a block diagram of a conventional computer address translation system. As shown in FIG. 1, first a 32-bit effect address EA is computed by passing through an effective address computational device 10. For example, the base address, offset address and the index address are summed together to obtain an effective address EA within the effective address computational device 10. Next, a selector address SA is input to a segment descriptor cache memory 11, and a 32-bit segment base address Base is output from it. Subsequently, the 32-bit segment base address and the effective address EA are added together to obtain a 32-bit linear address LA. The physical address PA can be determined only after the linear address LA has gone through the inquiries inside a translation lookaside buffer (TLB) 12. For example, the 0-11 bits of the linear address is a segment address, and the 12-bits of the linear address is page address. The page address is input to a tag memory 13 within the translation lookaside buffer (TLB) 12, and then compared with the linear address LA' there. If there is a hit that corresponds to the page base (PB) of the physical address stored in a data memory 14, the 20-bit physical page address is output and then combined with the original 12-bit segment address to form a physical address PA. The data memory 14 also resides within the translation lookaside buffer (TLB) 12 and can be a random access memory (RAM), for example. In other words, a linear address can be obtained only after an effective address is produced, and a physical address can be obtained only after the linear address is released, and hence much processing time is wasted. Because the address stored inside the linear address LA' of the tag memory 13 within the translation lookaside buffer (TLB) 12 is access serially, such processing will generate a critical path, and create a bottleneck in high speed electronic circuit designs.
In light of the foregoing, there is a need in the art for reducing the bottleneck in a conventional computer address translation system.